SH7670 Datasheet, PDF (503/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name value R/W Description
30
RDLE
0
R/W Receive Descriptor List Last
After completion of the corresponding buffer transfer,
the E-DMAC references the first receive descriptor.
This specification is used to set a ring configuration for
the receive descriptors.
0: This is not the last receive descriptor list
1: This is the last receive descriptor list
29, 28 RFP[1:0] 00
R/W Receive Frame Position
These two bits specify the relationship between the
receive buffer and receive frame.
00: Frame reception for receive buffer indicated by this
descriptor continues (frame is not concluded)
01: Receive buffer indicated by this descriptor
contains end of frame (frame is concluded)
10: Receive buffer indicated by this descriptor is start
of frame (frame is not concluded)
11: Contents of receive buffer indicated by this
descriptor are equivalent to one frame (one
frame/one buffer)
27
RFE
0
R/W Receive Frame Error
Indicates that one or other bit of the receive frame
status indicated by bits 25 to 16 is set. Whether or not
the receive frame status information is copied into this
bit is specified by the transmit/receive status copy
enable register.
0: No error during reception
1: A certain kind of error occurred during reception
26
RCSE
0
R/W Determination of Receive Packet Checksum Value
When CSEBL = 1 and CSMD = 1, the setting shown in
table 13.1 occurs depending on the received packet
and data.
The information in this bit will be invalid if operation is
based on any setting other than the above.
Rev. 1.00 Nov. 14, 2007 Page 477 of 1262
REJ09B0437-0100