SH7670 Datasheet, PDF (392/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 10 Watchdog Timer (WDT)
10.3.3 Watchdog Reset Control/Status Register (WRCSR)
WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal
generated by watchdog timer counter (WTCNT) overflow.
WRCSR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by
the internal reset signal generated by overflow of the WDT. WRCSR is initialized to H'1F in
software standby mode.
Note: The method for writing to WRCSR differs from that for other registers to prevent
erroneous writes. See section 10.3.4, Notes on Register Access, for details.
Bit: 7
6
5
4
3
2
1
0
WOVF RSTE RSTS -
-
-
-
-
Initial value: 0
0
0
1
1
1
1
1
R/W: R/(W) R/W R/W R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
7
WOVF
0
R/(W) Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval
timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
[Clearing condition]
• When 0 is written to WOVF after reading WOVF
6
RSTE
0
R/W Reset Enable
Selects whether to generate a signal to reset the LSI
internally if WTCNT overflows in watchdog timer
mode. In interval timer mode, this setting is ignored.
0: Not reset when WTCNT overflows*
1: Reset when WTCNT overflows
Note: * LSI not reset internally, but WTCNT and
WTCSR reset within WDT.
Rev. 1.00 Nov. 14, 2007 Page 366 of 1262
REJ09B0437-0100