SH7670 Datasheet, PDF (149/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 5 Exception Handling
5.6 Exceptions Triggered by Instructions
5.6.1 Types of Exceptions Triggered by Instructions
Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal
instructions, and integer division exceptions, as shown in table 5.10.
Table 5.10 Types of Exceptions Triggered by Instructions
Type
Trap instruction
Slot illegal
instructions
General illegal
instructions
Integer division
exceptions
Source Instruction
Comment
TRAPA
Undefined code placed
Delayed branch instructions: JMP, JSR,
immediately after a delayed
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
branch instruction (delay slot) BRAF
(including the FPU instruction and _{Instructions that rewrite the PC: JMP, JSR,}
FPU-related CPU instruction in _{BRA, BSR, RTS, RTE, BT, BF, TRAPA,}
FPU module standby mode),
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N
instructions that rewrite the PC,
32-bit instructions, RESBANK ^{32-bit instructions: BAND.B, BANDNOT.B,}
instruction, DIVS instruction, and ^{BCLR.B, BLD.B, BLDNOT.B, BOR.B,}
DIVU instruction
BORNOT.B, BSET.B, BST.B, BXOR.B,
MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S,
MOVU.B, MOVU.W.
Undefined code anywhere
besides in a delay slot (including
the FPU instruction and FPU-
related CPU instruction in FPU
module standby mode)
Division by zero
DIVU, DIVS
Negative maximum value ÷ (−1) DIVS
Floating-point
operation
instruction
Instructions that will cause Invalid FADD, FSUB, FMUL, FDIV, FMAC,
Operation Exception or Divide by FCMP/EQ, FCMP/GT, FLOAT,
Zero Exception defined in the FTRC,FCNVDS, FCNVSD, FSQRT
IEEE754 standard, and
instructions that may cause
Overflow Exception, Underflow
Exception, or Incorrectness
Exception
Rev. 1.00 Nov. 14, 2007 Page 123 of 1262
REJ09B0437-0100