SH7670 Datasheet, PDF (593/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
15.3.13 STIF Lock Control Register (STLKCR)
STLKCR is a 32-bit register to control PLL frequency lock. STLKCR is initialized to H'00000000
by a power-on reset.
Bit
Bit Name
31 to 26 
Initial
Value
All 0
25
LKWP
0
24
ULWP
0
23
ULCNT3 0
22
ULCNT2 0
21
ULCNT1 0
20
ULCNT0 0
19
LKCNT3 0
18
LKCNT2 0
17
LKCNT1 0
16
LKCNT0 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Setting this bit to 1 causes the LKCNT value to be
reflected in the internal LKCNT.
If this operation conflicts with the count up or clear
operation of the internal LKCNT, writing by LKWP takes
precedence.
This bit is automatically cleared to 0.
R/W Setting this bit to 1 causes the ULCNT value to be
reflected in the internal ULCNT.
If this operation conflicts with the count up or clear
operation of the internal ULCNT, writing by ULWP takes
precedence.
This bit is automatically cleared to 0.
R/W Setting ULWP to 1 causes the ULCNT value to be written
R/W ^{to the internal ULCNT. When read, these bits indicate the}
state below.
R/W
- The count of continuous LKZF = 1 states (outside the
R/W _{threshold value range) in the PLL lock state (LKF = 1)}
These bits are cleared to 0 when (1) ULCNT >= ULREF
(when LKF = 1, it is cleared to 0), (2) the ULCNT value
falls within the threshold value range (LKZF = 0), or (3)
"discont" occurs.
R/W Setting LKLP to 1 causes the LKCNT value to be written
R/W ^{to the internal LKCNT. When read, these bits indicate the}
state below.
R/W
- The count of continuous LKZF = 0 states (within the
R/W _{threshold value range) in the PLL unlock state (LKF = 0)}
These bits are cleared to 0 when (1) LKCNT >= LKREF
(when LKF = 0, it is set to 1) , (2) the LKCNT value
exceeds the threshold value range (LKZF = 1), or (3)
"discont" occurs.
Rev. 1.00 Nov. 14, 2007 Page 567 of 1262
REJ09B0437-0100