SH7670 Datasheet, PDF (447/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 12 Ethernet Controller (EtherC)
12.3.19 IPG Register (IPGR)
IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting
and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to
section 12.4.6, Operation by IPG Setting.)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
IPG[4:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W
Bit Bit Name
31 to 5 
4 to 0 IPG[4:0]
Initial
Value
All 0
H'13
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Inter Packet Gap
Sets the IPG value every 4-bit time.
H'00: 20-bit time
H'01: 24-bit time
:
:
H'13: 96-bit time (Initial value)
:
:
H'1F: 144-bit time
Rev. 1.00 Nov. 14, 2007 Page 421 of 1262
REJ09B0437-0100