SH7670 Datasheet, PDF (395/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 10 Watchdog Timer (WDT)
10.4 WDT Usage
10.4.1 Canceling Software Standby Mode
The WDT can be used to cancel software standby mode with an interrupt such as an NMI
interrupt. The procedure is described below. (The WDT does not operate when resets are used for
canceling, so keep the RES pin low until clock oscillation settles.)
1. Before making a transition to software standby mode, always clear the TME bit in WTCSR
to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated
when the count overflows.
2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the
counter in WTCNT. These values should ensure that the time till count overflow is longer than
the clock oscillation settling time.
3. After setting the STBY bit of the standby control register (STBCR: see section 11, Power-
Down Modes) to 1, the execution of a SLEEP instruction puts the system in software standby
mode and clock operation then stops.
4. The WDT starts counting by detecting the edge change of the NMI signal.
5. When the WDT count overflows, the CPG starts supplying the clock and this LSI resumes
operation. The WOVF flag in WRCSR is not set when this happens.
10.4.2 Changing the Frequency
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the
counter in WTCNT. These values should ensure that the time till count overflow is longer than
the clock oscillation settling time. However, the WDT counts up using the clock after the
setting.
3. When the frequency control register (FRQCR) is written to, this LSI stops temporarily. The
WDT starts counting.
4. When the WDT count overflows, the CPG resumes supplying the clock and this LSI resumes
operation. The WOVF flag in WRCSR is not set when this happens.
Rev. 1.00 Nov. 14, 2007 Page 369 of 1262
REJ09B0437-0100