SH7670 Datasheet, PDF (567/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
FEC operation start descriptor (2 source rows/column processing)
FECD00_SZ[15:0] = XOR operation data size
FECD00_SN[3:0] = H'2
FECD00_DRE = 0
FECD00_F2
=0
FECD00_F0
=1
FEC operation middle descriptor (2 source rows/column processing)
FECD00_SZ[15:0] = XOR operation data size
FECD00_SN[3:0] = H'2
FECD00_DRE = 1
FECD00_F2
=0
FECD00_F0
=1
FEC operation last descriptor (1 source rows/column processing)
FECD00_SZ[15:0] = XOR operation data size
FECD00_SN[3:0] = H'1
FECD00_DRE = 1
FECD00_F2
=1
FECD00_F0
=1
Invalid descriptor
FECD00_F0
=0
Figure 14.5 Example of FEC Descriptor Configuration
Rev. 1.00 Nov. 14, 2007 Page 541 of 1262
REJ09B0437-0100