SH7670 Datasheet, PDF (672/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
4
UACT
0
R/W USB Bus Enable
Enables operation of the USB bus (controls the SOF
or µSOF packet transmission to the USB bus) when
the host controller function is selected.
0: Downstream port is disabled (SOF/µSOF
transmission is disabled).
1: Downstream port is enabled (SOF/µSOF
transmission is enabled).
With this bit set to 1, this module puts the USB port
to the USB-bus enabled state and performs SOF
output and data transmission and reception.
This module starts outputting SOF/µSOF within 1 (µ)
frame after software has written 1 to UACT.
With this bit set to 0, this module enters the idle state
after outputting SOF/µSOF.
This module sets this bit to 0 on any of the following
conditions.
• A DTCH interrupt is detected during
communication (while UACT = 1).
• An EOFERR interrupt is detected during
communication (while UACT = 1).
Writing 1 to this bit should be done at the end of the
USB reset process (writing 0 to USBRST) or at the
end of the resume process from the suspended state
(writing 0 to RESUME).
This bit should be set to 0 if the function controller
function is selected.
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 14, 2007 Page 646 of 1262
REJ09B0437-0100