SH7670 Datasheet, PDF (470/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.2.5 Receive Descriptor List Address Register (RDLAR)
RDLAR is a 32-bit readable/writable register that specifies the start address of the receive
descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length
indicated by the DL bit in EDMR. This register must not be written to during reception.
Modifications to this register should only be made while reception is disabled by the RR bit (= 0)
in the E-DMAC Receive Request Register (EDRRR).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDLA[31:16]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RDLA[15:0]
Initial Value: ⁰
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
31 to 0 RDLA[31:0] All 0
R/W Receive Descriptor Start Address
The lower bits are set as follows according to the
specified descriptor length.
16-byte boundary: RDLA3 to RDLA0 = 0000
32-byte boundary: RDLA4 to RDLA0 = 00000
64-byte boundary: RDLA5 to RDLA0 = 000000
Rev. 1.00 Nov. 14, 2007 Page 444 of 1262
REJ09B0437-0100