SH7670 Datasheet, PDF (1288/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Slave transmit operation ......................... 856
Sleep mode ............................................. 389
Slot illegal instructions ........................... 124
Software standby mode .......................... 390
SRAM interface with byte selection....... 272
SSI Module Timing .............................. 1222
Stack after interrupt
exception handling.................................. 154
Stack status after
exception handling ends ......................... 128
Standby control circuit............................ 346
Status register (SR)................................... 30
STIF ModuleSignal Timing.................. 1239
Supported DMA transfers....................... 330
System control instructions ...................... 65
T
T bit .......................................................... 37
TAP controller ...................................... 1087
TDO output timing ............................... 1089
Timing to clear an interrupt source......... 168
Transceiver Timing............................... 1225
Transfer rate............................................ 838
Transmit descriptor 0 (TD0)................... 471
Transmit descriptor 1 (TD1)................... 474
Transmit descriptor 2 (TD2)................... 474
Trap instructions ..................................... 124
Types of exception handling and
priority order ........................................... 107
U
Unconditional branch instructions with
no delay slot.............................................. 37
USB 2.0 host/function module (USB) .... 623
User break controller (UBC)................. 1063
User break interrupt ................................ 143
Using interval timer mode ...................... 372
Using watchdog timer mode ................... 370
V
Vector base register (VBR)....................... 31
W
Wait between access cycles .................... 284
Watchdog timer (WDT).......................... 361
Watchdog Timer Timing....................... 1217
Write-back buffer
(only for operand cache) ........................... 99
Rev. 1.00 Nov. 14, 2007 Page 1262 of 1262
REJ09B0437-0100