SH7670 Datasheet, PDF (426/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 12 Ethernet Controller (EtherC)
12.3.1 EtherC Mode Register (ECMR)
ECMR is a 32-bit readable/writable register and specifies the operating mode of the Ethernet
controller. The settings in this register are normally made in the initialization process following a
reset.
The operating mode setting must not be changed while the transmitting and receiving functions
are enabled. To switch the operating mode, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
-
-
-
-
ZPF PFR RXF TXF
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
-
-
- PRCEF -
-
Initial value: 0
0
0
0
0
0
R/W: R
R
R
R/W
R
R
Initial
Bit
Bit Name Value R/W
31 to 20 
All 0
R
19
ZPF
0
R/W
9
8
MPDE -
0
0
R/W
R
7
6
5
4
3
2
1
0
-
RE
TE
-
ILB ELB DM PRM
0
0
0
0
0
0
0
0
R
R/W R/W
R
R/W R/W R/W R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
0 time parameter PAUSE Frame Use Enable
0: Disables PAUSE frame control in which the TIME
parameter is 0.
The next frame is transmitted after the time
indicated by the Timer value has elapsed. When the
EtherC receives a PAUSE frame with the time
indicated by the Timer value set to 0, the PAUSE
frame is discarded.
1: Enables PAUSE frame control in which the TIME
parameter is 0.
A PAUSE frame with the Timer value set to 0 is
transmitted when the number of data in the receive
FIFO is less than the FCFTR value before the time
indicated by the Timer value has not elapsed. When
the EtherC receives a PAUSE frame with the time
indicated by the Timer value set to 0, the transmit
wait state is canceled.
Rev. 1.00 Nov. 14, 2007 Page 400 of 1262
REJ09B0437-0100