SH7670 Datasheet, PDF(352/1292 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

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SH7670 Datasheet, PDF (352/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

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Section 8 Direct Memory Access Controller (DMAC)

Table 8.8 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits

CHCR DMARS DMA Transfer

Request

RS[3:0] MID RID Source

DMA Transfer

Request Signal

Transfer

Source

Transfer

Destination Bus Mode

1000 000000 11 USB

USB_DMA0

(receive FIFO full)

D0FIFO

Any

Cycle steal

or burst

USB_DMA0

Any

(transmit FIFO empty)

D0FIFO

000001 11 USB

USB_DMA1

(receive FIFO full)

D1FIFO

Any

USB_DMA1

Any

(transmit FIFO empty)

D1FIFO

000100 01 SDHI transmit TXI (receive data empty) Data register Any

Cycle steal

10 SDHI receive RXI (transmit data full)

Any

Data

register

001000 11 SSI_0

DMA0 (transmit mode)

DMA0 (receive mode)

Any

SSIRDR0

SSITDR0

Any

Cycle steal

or burst

001001 11 SSI_1

DMA1 (transmit mode)

Any

SSITDR1

DMA1 (receive mode)

SSIRDR1 Any

011000 01 IIC3_0 transmit TXI0 (transmit data empty) Any

ICDRT0

Cycle steal

10 IIC3_0 receive RXI0 (receive data full)

ICDRR0

Any

100000 01 SCIF_0 transmit TXI0

Any

(transmit FIFO data empty)

SCFTDR_0

10 SCIF_0 receive RXI0

(receive FIFO data full)

SCFRDR_0 Any

100001 01 SCIF_1 transmit TXI1

Any

(transmit FIFO data empty)

SCFTDR_1

10 SCIF_1 receive RXI1

(receive FIFO data full)

SCFRDR_1 Any

100010 01 SCIF_2 transmit TXI2

Any

(transmit FIFO data empty)

SCFTDR_2

10 SCIF_2 receive RXI2

(receive FIFO data full)

SCFRDR_2 Any

111110 11 CMT_0

CMI0 (compare match)

Any

Any

Cycle steal

111111 11 CMT_1

CMI1 (compare match)

Any

Any

or burst

Rev. 1.00 Nov. 14, 2007 Page 326 of 1262

REJ09B0437-0100

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