SH7670 Datasheet, PDF (354/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 8 Direct Memory Access Controller (DMAC)
(1) When channel 0 transfers
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Channel 0 is given the lowest priority
among the round-robin channels.
Priority order
after transfer
CH1 > CH2 > CH3 > CH0 > CH4 > CH5 > CH6 > CH7
(2) When channel 1 transfers
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Channel 1 is given the lowest priority
among the round-robin channels. The
priority of channel 0, which was higher
than channel 1, is also shifted.
Priority order
after transfer
CH2 > CH3 > CH0 > CH1 > CH4 > CH5 > CH6 > CH7
(3) When channel 2 transfers
Initial priority order
Priority order
after transfer
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
CH3 > CH0 > CH1 > CH2 > CH4 > CH5 > CH6 > CH7
Channel 2 is given the lowest priority
among the round-robin channels. The
priority of channels 0 and 1, which were
higher than channel 2, is also shifted. If
there is a transfer request only to
channel 5 immediately after that, the
priority does not change because
channel 5 is not a round-robin channel.
Post-transfer priority order
when there is an
immediate transfer
request to channel 5 only
CH3 > CH0 > CH1 > CH2 > CH4 > CH5 > CH6 > CH7
(4) When channel 7 transfers
Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Priority order does not change.
Priority order
after transfer
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Figure 8.3 Round-Robin Mode
Rev. 1.00 Nov. 14, 2007 Page 328 of 1262
REJ09B0437-0100