SH7670 Datasheet, PDF (94/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 2 CPU
Instruction
Instruction Code
FMOV.S @(R0, Rm), FRn 1111nnnnmmmm0110
FMOV.D @(R0, Rm), DRn 1111nnn0mmmm0110
FMOV.S @Rm+, FRn
1111nnnnmmmm1001
FMOV.D @Rm+, DRn
1111nnn0mmmm1001
FMOV.S @Rm, FRn
1111nnnnmmmm1000
FMOV.D @Rm, DRn
1111nnn0mmmm1000
FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001
0111dddddddddddd
FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001
0111dddddddddddd
FMOV.S FRm, @(R0,Rn) 1111nnnnmmmm0111
FMOV.D DRm, @(R0,Rn) 1111nnnnmmm00111
FMOV.S FRm, @-Rn
1111nnnnmmmm1011
FMOV.D DRm, @-Rn
1111nnnnmmm01011
FMOV.S FRm, @Rn
1111nnnnmmmm1010
FMOV.D DRm, @Rn
1111nnnnmmm01010
FMOV.S FRm,
@(disp12,Rn)
0011nnnnmmmm0001
0011dddddddddddd
FMOV.D DRm,
@(disp12,Rn)
0011nnnnmmm00001
0011dddddddddddd
FMUL FRm, FRn
1111nnnnmmmm0010
FMUL DRm, DRn
1111nnn0mmm00010
FNEG FRn
1111nnnn01001101
FNEG DRn
1111nnn001001101
FSCHG
1111001111111101
FSQRT
FSQRT
FSTS
FSUB
FRn
DRn
FPUL,FRn
FRm, FRn
1111nnnn01101101
1111nnn001101101
1111nnnn00001101
1111nnnnmmmm0001
Compatibility
Operation
Execu-
tion
Cycles T Bit
SH2E SH4
SH-2A/
SH2A-
FPU
(R0 + Rm) → FRn
1

Yes Yes Yes
(R0 + Rm) → DRn
2

Yes Yes
(Rm) → FRn, Rm+=4 1

Yes Yes Yes
(Rm) → DRn, Rm += 8 2

Yes Yes
(Rm) → FRn
1

Yes Yes Yes
(Rm) → DRn
2

Yes Yes
(disp × 4 + Rm) → FRn 1

Yes
(disp × 8 + Rm) → DRn 2

Yes
FRm → (R0 + Rn)
1
DRm → (R0 + Rn)
2
Rn-=4, FRm → (Rn)
1
Rn-=8, DRm → (Rn) 2
FRm → (Rn)
1
DRm → (Rn)
2
FRm → (disp × 4 + Rn) 1

Yes Yes Yes

Yes Yes

Yes Yes Yes

Yes Yes

Yes Yes Yes

Yes Yes

Yes
DRm → (disp × 8 + Rn) 2

Yes
FRn × FRm → FRn
1

Yes Yes Yes
DRn × DRm → DRn
6

Yes Yes
-FRn → FRn
1

Yes Yes Yes
-DRn → DRn
1

Yes Yes
FPSCR.SZ=~FPSCR.S 1

Z
Yes Yes
√FRn → FRn
9

Yes Yes
√DRn → DRn
22

Yes Yes
FPUL → FRn
1

Yes Yes Yes
FRn-FRm → FRn
1

Yes Yes Yes
Rev. 1.00 Nov. 14, 2007 Page 68 of 1262
REJ09B0437-0100