SH7670 Datasheet, PDF (451/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 12 Ethernet Controller (EtherC)
12.4 Operation
The overview of the Ethernet controller (EtherC) are shown below. The EtherC transmits and
receives PAUSE frames conforming to the Ethernet/IEEE802.3 frames.
12.4.1 Transmission
The EtherC transmitter assembles the transmit data on the frame and outputs to MII when there is
a transmit request from the E-DMAC. The data transmitted via the MII is transmitted to the lines
by PHY-LSI. Figure 12.3 shows the state transition of the EtherC transmitter.
Rev. 1.00 Nov. 14, 2007 Page 425 of 1262
REJ09B0437-0100