SH7670 Datasheet, PDF (578/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
15.3.3 STIF Internal Counter Control Register (STCNTCR)
STCNTCR is a 32-bit register to control the internal counter for timestamp. STCNTCR is
initialized to H'00000000 by a power-on reset.
Bit Bit Name
31 to 4 
3
CRD
2
CSTP
1
CSET
0
CRST
Initial
Value
All 0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Setting this bit to 1 causes the internal counter value for
timestamp to be read to STCNTVR.
This bit is automatically cleared to 0.
Stops the internal counter for timestamp.
0: Count operation is continued.
1: Counter is stopped with its value retained.
Setting this bit to 1 causes the STCNTVR value to be
reloaded to the internal counter for timestamp.
This bit is automatically cleared to 0.
Setting this bit to 1 causes the internal counter for
timestamp to be initialized to H'00000000.
This bit is automatically cleared to 0.
Rev. 1.00 Nov. 14, 2007 Page 552 of 1262
REJ09B0437-0100