SH7670 Datasheet, PDF (464/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.2 Register Descriptions
The E-DMAC has the following registers. For addresses and access sizes of these registers, see
section 28, List of Registers.
• E-DMAC mode register (EDMR)
• E-DMAC transmit request register (EDTRR)
• E-DMAC receive request register (EDRRR)
• Transmit descriptor list address register (TDLAR)
• Receive descriptor list address register (RDLAR)
• EtherC/E-DMAC status register (EESR)
• EtherC/E-DMAC status interrupt permission register (EESIPR)
• Transmit/receive status copy enable register (TRSCER)
• Receive missed-frame counter register (RMFCR)
• Transmit FIFO threshold register (TFTR)
• FIFO depth register (FDR)
• Receiving method control register (RMCR)
• E-DMAC operation control register (EDOCR)
• Receive buffer write address register (RBWAR)
• Receive descriptor fetch address register (RDFAR)
• Transmit buffer read address register (TBRAR)
• Transmit descriptor fetch address register (TDFAR)
• Flow control FIFO threshold register (FCFTR)
• Receive data padding setting register (RPADIR)
• Transmit interrupt register (TRIMD)
• Checksum mode register (CSMR)
• Checksum skipped bytes monitor register (CSSBM)
• Checksum monitor register (CSSMR)
Rev. 1.00 Nov. 14, 2007 Page 438 of 1262
REJ09B0437-0100