SH7670 Datasheet, PDF (112/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 3 Floating-Point Unit (FPU)
3.5.2 FPU Exception Handling
FPU exception handling is initiated in the following cases:
• FPU error (E): FPSCR.DN = 0 and a denormalized number is input (No error occurs in the
SH2A-FPU)
• Invalid operation (V): FPSCR.Enable.V = 1 and invalid operation
• Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor
• Overflow (O): FPSCR.Enable.O = 1 and instruction with possibility of operation result
overflow
• Underflow (U): FPSCR.Enable.U = 1 and instruction with possibility of operation result
underflow
• Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation
result
These possibilities are shown in the individual instruction descriptions. All exception events that
originate in the FPU are assigned as the same exception event. The meaning of an exception is
determined by software by reading from FPSCR and interpreting the information it contains. If no
bits are set in the FPU exception cause field of FPSCR when one or more of bits O, U, I, and V are
set in the FPU exception enable field, this indicates that an actual exception source is not
generated. Also, the destination register is not changed by any FPU exception handling operation.
Except for the above, the FPU disables exception handling. In every processing, the bit
corresponding to source V, Z, O, U, or I is set to 1, and a default value is generated as the
operation result.
• Invalid operation (V): qNaN is generated as the result.
• Division by zero (Z): Infinity with the same sign as the unrounded value is generated.
• Overflow (O):
When rounding mode = RZ, the maximum normalized number, with the same sign as the
unrounded value, is generated.
When rounding mode = RN, infinity with the same sign as the unrounded value is generated.
• Underflow (U):
Zero with the same sign as the unrounded value is generated.
• Inexact exception (I): An inexact result is generated.
Rev. 1.00 Nov. 14, 2007 Page 86 of 1262
REJ09B0437-0100