SH7670 Datasheet, PDF (572/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
15.3 Register Descriptions
The STIF has the following registers. For the address and status at each processing state of these
registers, see section 28, List of Registers.
• STIF mode select register (STMDR_0)
• STIF control register (STCTLR_0)
• STIF internal counter control register (STCNTCR_0)
• STIF internal counter set register (STCNTVR_0)
• STIF status register (STSTR_0)
• STIF interrupt enable register (STIER_0)
• STIF transfer size register (STSIZER_0)
• STIFPWM mode register (STPWMMR_0)
• STIFPWM control register_0 (STPWMCR_0)
• STIFPWM register (STPWMR_0)
• STIFPCR0 register (STPCR0R_0)
• STIFPCR1 register (STPCR1R_0)
• STIFSTC0 register (STSTC0R_0)
• STIFSTC1 register (STSTC1R_0)
• STIF lock control register (STLKCR_0)
• STIF debugging status register (STDBGR_0)
• STIF mode select register (STMDR_1)
• STIF control register (STCTLR_1)
• STIF internal counter control register (STCNTCR_1
• STIF internal counter set register (STCNTVR_1)
• STIF status register (STSTR_1)
• STIF interrupt enable register (STIER_1)
• STIF transfer size register (STSIZER_1)
• STIFPWM mode register (STPWMMR_1)
• STIFPWM control register_1 (STPWMCR_1)
• STIFPWM register (STPWMR_1)
• STIFPCR0 register (STPCR0R_1)
• STIFPCR1 register (STPCR1R_1)
• STIFSTC0 register (STSTC0R_1)
• STIFSTC1 register (STSTC1R_1)
Rev. 1.00 Nov. 14, 2007 Page 546 of 1262
REJ09B0437-0100