SH7670 Datasheet, PDF (528/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
14.2.2 Channel [i] Processing Mode Register (C[i]M) (i = 0, 1)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0











C[i]M_
LIE




Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R
R
R
R
Bit
Bit Name
31 to 5 —
4
C[i]M_LIE
3 to 0 —
Initial
Value R/W
All 0 R
0
R/W
All 0 R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
"Last Data Descriptor End Processing" Interrupt
Request Enable
When last data (C[i]F2=1) descriptor end processing
ends, specifies whether to enable or disable the
interrupt request.
0: Disables the "last data descriptor processing
end" interrupt request.
1: Enables the "last data descriptor processing end"
interrupt request.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 14, 2007 Page 502 of 1262
REJ09B0437-0100