SH7670 Datasheet, PDF (918/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W Description
31 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7 to 1 
All 0
R/W AC-Bit Writing Assistance
These bits should be used to write the bit pattern (H'A5)
needed to set the AC bit to 1. These bits are always
read as 0.
0
AC
0/1
R/W HIFRAM Access Exclusive Control
Controls accessing of HIFRAM by the on-chip CPU for
the HIFRAM bank selected by the BMD and BSEL bits
in HIFSCR as the bank allowed to be accessed by this
LSI.
0: The on-chip CPU can perform reading/writing of
HIFRAM.
1: When an HIFRAM read/write operation by the on-chip
CPU occurs, the CPU enters the wait state, and
execution of the instruction is halted until this bit is
cleared to 0.
When booted in non-HIF boot mode, the initial value of
this bit is 0.
When booted in HIF boot mode, the initial value of this
bit is 1. After an external device writes a boot program to
HIFRAM via the HIF, clearing this bit to 0 boots the on-
chip CPU from HIFRAM.
When 1 is written to this bit by an external device, H'A5
should be written to bits 7 to 0 to prevent erroneous
writing.
Rev. 1.00 Nov. 14, 2007 Page 892 of 1262
REJ09B0437-0100