SH7670 Datasheet, PDF (217/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Bit
6
5 to 2
1, 0
Section 7 Bus State Controller (BSC)
Bit Name
WM
Initial
Value
0

All 0
HW[1:0] 00
R/W Description
R/W External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Delay Cycles from RD, WEn Negation to Address, CS4
Negation
Specify the number of delay cycles from RD and WEn
negation to address and CS4 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 1.00 Nov. 14, 2007 Page 191 of 1262
REJ09B0437-0100