SH7670 Datasheet, PDF (265/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
Table 7.12 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address
Multiplex Output (2)-2
Setting
BSZ[1:0]
A3ROW[1:0] A3COL[1:0]
11 (32 bits) 01 (12 bits)
10 (10 bits)
Output Pin of Row Address Column Address
This LSI
Output
Output
SDRAM Pin
Function
A17
A27
A17
Unused
A16
A26
A16
A15
A25*²
A25*²
A14
A24*²
A24*²
A13 (BA1)
A12 (BA0)
Specifies bank
A13
A23
A12
A22
A13
L/H*¹
A11
A10/AP
Address
Specifies
address/precharge
A11
A21
A11
A9
Address
A10
A20
A10
A8
A9
A19
A9
A7
A8
A18
A8
A6
A7
A17
A7
A5
A6
A16
A6
A4
A5
A15
A5
A3
A4
A14
A4
A2
A3
A13
A3
A1
A2
A12
A2
A0
A1
A11
A1
Unused
A0
A10
A0
Example of connected memory
512-Mbit product (4 Mwords × 32 bits × 4 banks, column 10 bits product): 1
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
Rev. 1.00 Nov. 14, 2007 Page 239 of 1262
REJ09B0437-0100