SH7670 Datasheet, PDF (524/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
14.2 Register Descriptions
The A-DMAC has the following registers. For details on the addresses of these registers and the
register status in each processing state, see section 28, List of Registers.
• Channel [i] processing control register (C[i]C) (i = 0, 1)
• Channel [i] processing mode register (C[i]M) (i = 0, 1)
• Channel [i] processing interrupt request register (C[i]I) (i = 0, 1)
• Channel [i] processing descriptor start address register (C[i]DSA) (i = 0, 1)
• Channel [i] processing descriptor current address register (C[i]DCA) (i = 0, 1)
• Channel [i] processing descriptor 0 register (C[i]D0) [control] (i = 0, 1)
• Channel [i] processing descriptor 1 register (C[i]D1) [source address] (i = 0, 1)
• Channel [i] processing descriptor 2 register (C[i]D2) [destination address] (i = 0, 1)
• Channel [i] processing descriptor 3 register (C[i]D3) [data length] (i = 0, 1)
• Channel [i] processing descriptor 4 register (C[i]D4) [checksum value write address] (i = 0, 1)
• FEC DMAC processing control register (FECC)
• FEC DMAC processing interrupt request register (FECI)
• FEC DMAC processing descriptor start address register (FECDSA)
• FEC DMAC processing descriptor current address register (FECDCA)
• FEC DMAC processing descriptor 0 register (FECD00) [control]
• FEC DMAC processing descriptor 1 register (FECD01D0A) [destination address]
• FEC DMAC processing descriptor 2 register (FECD02S0A) [source 0 address]
• FEC DMAC processing descriptor 3 register (FECD03S1A) [source 1 address]
Rev. 1.00 Nov. 14, 2007 Page 498 of 1262
REJ09B0437-0100