SH7670 Datasheet, PDF (992/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Figure 22.3 shows a sample flowchart for initializing the SCIF.
Start of initialization
Clear TE and RE bits in SCSCR to 0
Set TFRST and RFRST bits in SCFCR to 1
After reading ER, DR, and BRK flags in SCFSR,
and each flag in SCLSR, write 0 to clear them
Set CKE[1:0] in SCSCR
(leaving TIE, RIE, TE, and RE bits cleared to 0)
[1]
Set data transfer format in SCSMR
[2]
Set value in SCBRR
[3]
Set RTRG[1:0], TTRG[1:0], and MCE bits in
SCFCR, and clear TFRST and RFRST bits to 0
PFC setting for external pins used
[4]
SCK, TxD, RxD
Set TE and RE bits in SCSCR to 1,
and set TIE, RIE, and REIE bits
[5]
End of initialization
[1] Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
[2] Set the data transfer format in
SCSMR.
[3] Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
[4] Sets PFC for external pins used.
Set as RxD input at receiving and
TxD at transmission.
However, no setting for SCK pin is
required when CKE[1:0] is 00.
In the case when internal synchronous
clock output is set, the SCK pin starts
outputting the clock at this stage.
[5] Set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits. Setting the TE and RE bits
enables the TxD and RxD pins to be
used.
When transmitting, the SCIF will go
to the mark state; when receiving,
it will go to the idle state, waiting for
a start bit.
Figure 22.3 Sample Flowchart for SCIF Initialization
Rev. 1.00 Nov. 14, 2007 Page 966 of 1262
REJ09B0437-0100