SH7670 Datasheet, PDF (331/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 8 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
21

0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
20
TEMASK 0
R/W TE Set Mask
Indicates that DMA transfer is not terminated when the
TE bit is set to 1. By setting this bit together with the
SAR reload function or the DAR reload function, DMA
transfer can be executed until the transfer request is
canceled. Upon detection of the rising or falling edge of
an auto request or external request, this bit is ignored
and the DMA transfer is terminated when the TE bit is
set. Note that this function is enabled if either of the
RLDSAR bit or the RLDDAR bit is set to 1.
0: Terminates DMA if the TE bit is set.
1: Continues DMA even if the TE bit is set.
19
HE
0
R/(W)* Half-End Flag
This bit is set to 1 when the transfer count reaches half
of the DMATCR value that was specified before
transfer starts.
If DMA transfer ends because of an NMI interrupt, a
DMA address error, or clearing of the DE bit or the
DME bit in DMAOR before the transfer count reaches
half of the initial DMATCR value, the HE bit is not set to
1. If DMA transfer ends due to an NMI interrupt, a DMA
address error, or clearing of the DE bit or the DME bit
in DMAOR after the HE bit is set to 1, the bit remains
set to 1.
To clear the HE bit, write 0 to it after HE = 1 is read.
0: DMATCR > (DMATCR set before transfer starts)/2
during DMA transfer or after DMA transfer is
terminated
[Clearing condition]
• Writing 0 after reading HE = 1.
1: DMATCR ≤ (DMATCR set before transfer starts)/2
Rev. 1.00 Nov. 14, 2007 Page 305 of 1262
REJ09B0437-0100