SH7670 Datasheet, PDF (361/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 8 Direct Memory Access Controller (DMAC)
DREQ
Bus mastership returned to CPU once
Bus cycle
CPU
CPU CPU DMAC DMAC CPU DMAC DMAC CPU
Read/Write
Read/Write
Figure 8.9 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection)
• Intermittent Mode 16 and Intermittent Mode 64
In intermittent mode of cycle steal, DMAC returns the bus mastership to other bus master
whenever a unit of transfer (byte, word, longword, or 16 bytes) is completed. If the next
transfer request occurs after that, DMAC obtains the bus mastership from other bus master
after waiting for 16 or 64 cycles of Bφ clock. DMAC then transfers data of one unit and returns
the bus mastership to other bus master. These operations are repeated until the transfer end
condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA
transfer than the normal mode of cycle steal.
When DMAC obtains again the bus mastership, DMA transfer may be postponed in case of
entry updating due to cache miss.
The cycle-steal intermittent mode can be used for any transfer section; transfer request source,
transfer source, and transfer destination. The bus modes, however, must be cycle steal mode in
all channels.
Figure 8.10 shows an example of DMA transfer timing in cycle-steal intermittent mode.
Transfer conditions shown in the figure are;
 Dual address mode
 DREQ low level detection
DREQ
More than 16 or 64 Bφ clock cycles
(depends on the CPU's condition of using bus)
Bus cycle
CPU CPU CPU DMAC DMAC CPU
Read/Write
CPU DMAC DMAC CPU
Read/Write
Figure 8.10 Example of DMA Transfer in Cycle-Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)
Rev. 1.00 Nov. 14, 2007 Page 335 of 1262
REJ09B0437-0100