SH7670 Datasheet, PDF (829/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
(b) REW Bit
It is possible to temporarily stop access to the pipe currently being accessed, access a different
pipe, and then continue processing using the current pipe once again. The REW bit in
C/DnFIFOSEL is used for this.
If a pipe is selected when the REW bit is set to 1 and at the same time the CURPIPE bit in
C/DnFIFOSEL is set, the pointer used for reading from and writing to the buffer memory is reset,
and reading or writing can be carried out from the first byte. Also, if a pipe is selected with 0 set
for the REW bit, data can be read and written in continuation of the previous selection, without the
pointer used for reading from and writing to the buffer memory being reset.
To access the FIFO port, FRDY = 1 must be ensured after selecting a pipe.
(3) DMA Transfers (D0FIFO/D1FIFO port)
(a) Overview of DMA Transfers
For pipes 1 to 9, the FIFO port can be accessed using the DMAC. When accessing the buffer for
the pipe targeted for DMA transfer is enabled, a DMA transfer request is issued.
The unit of transfer to the FIFO port should be selected using the MBW bit in DnFIFOSEL and
the pipe targeted for the DMA transfer should be selected using the CURPIPE bit. The selected
pipe should not be changed during the DMA transfer.
(b) Auto Recognition of DMA Transfer Completion
With this module, it is possible to complete FIFO data writing through DMA transfer by
controlling DMA transfer end signal input. When a transfer end signal is sampled, the module
enables buffer memory transmission (the same condition as when BVAL = 1).
(c) DnFIFO Auto Clear Mode (D0FIFO/D1FIFO Port Reading Direction)
If 1 is set for the DCLRM bit in DnFIFOSEL, the module automatically clears the buffer memory
of the selected pipe when reading of the data from the buffer memory has been completed.
Table 17.26 shows the packet reception and buffer memory clearing processing for each of the
various settings. As shown, the buffer clear conditions depend on the value set to the BFRE bit.
Using the DCLRM bit eliminates the need for the buffer to be cleared by software even if a
situation occurs that necessitates clearing of the buffer. This makes it possible to carry out DMA
transfers without involving software.
This function can be set only in the buffer memory reading direction.
Rev. 1.00 Nov. 14, 2007 Page 803 of 1262
REJ09B0437-0100