SH7670 Datasheet, PDF (390/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 10 Watchdog Timer (WDT)
10.3.2 Watchdog Timer Control/Status Register (WTCSR)
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, overflow flags, and timer enable bit.
WTCSR is initialized to H'18 by a power-on reset caused by the RES pin or in software standby
mode. When used to count the clock oscillation settling time for canceling software standby mode,
it retains its value after counter overflow.
Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from
WTCSR.
Note: The method for writing to WTCSR differs from that for other registers to prevent
erroneous writes. See section 10.3.4, Notes on Register Access, for details.
Bit: 7
6
5
4
IOVF WT/IT TME
-
Initial value: 0
0
0
1
R/W: R/(W) R/W R/W R
3
2
1
0
-
CKS[2:0]
1
0
0
0
R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
IOVF
0
R/(W) Interval Timer Overflow
Indicates that WTCNT has overflowed in interval timer
mode. This flag is not set in watchdog timer mode.
0: No overflow
1: WTCNT overflow in interval timer mode
[Clearing condition]
• When 0 is written to IOVF after reading IOVF
6
WT/IT
0
R/W Timer Mode Select
Selects whether to use the WDT as a watchdog timer
or an interval timer.
0: Use as interval timer
1: Use as watchdog timer
Note: When the WTCNT overflows in watchdog timer
mode, the WDTOVF signal is output externally.
If this bit is modified when the WDT is running,
the counting-up may not be performed
correctly.
Rev. 1.00 Nov. 14, 2007 Page 364 of 1262
REJ09B0437-0100