SH7670 Datasheet, PDF (708/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
17.3.17 Interrupt Status Register 1 (INTSTS1)
INTSTS1 is a register that is used to confirm interrupt status.
Interrupt generation can be confirmed simply by referencing one of the registers: INTSTS0 when
the function controller function is selected and INTSTS1 when the host controller function is
selected.
The various interrupts indicated by the bits in this register should be enabled only when the host
controller function is selected.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— BCHG — DTCH ATTCH —
—
—
—
EOF
ERR
SIGN SACK
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W*¹ R R/W*¹ R/W*¹ R
R
R
R R/W*¹ R/W*¹ R/W*¹ R
R
R
R
Initial
Bit
Bit Name
Value R/W Description
15

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14
BCHG
0
R/W*¹ USB Bus Change Interrupt Status
Indicates the status of the USB bus change interrupt.
0: BCHG interrupts not generated
1: BCHG interrupts generated
This module detects the BCHG interrupt when a
change in the full-speed or low-speed signal level
occurs on the USB port (a change from J-state, K-
state, or SE0 to J-state, K-state, or SE0), and sets this
bit to 1. Here, if software has set the corresponding
interrupt enable bit to 1, this module generates the
interrupt.
This module sets the LNST bits in SYSSTS0 to
indicate the current input state of the USB port. When
the BCHG interrupt is generated, use software to
repeat reading the LNST bits until the same value is
read three or more times, and eliminate chattering.
A change in the USB bus state can be detected even
while the internal clock supply is stopped.
When the function controller function is selected, the
read value is invalid.
Rev. 1.00 Nov. 14, 2007 Page 682 of 1262
REJ09B0437-0100