SH7670 Datasheet, PDF (534/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Bit
Bit Name
31 to 28 C[i]CRDO[3:0]
Initial
Value R/W
All 0 R/W
Description
• When the destination is not the STIF (C[i]DA bit
= 0)
C[i]CRDO3: Data swap in two-byte units
(longword swap in word units)
0: As-is
1: Swap
C[i]CRDO2: Data swap in one-byte units (word
swap in byte units)
0: As-is
1: Swap
C[i]CRDO1: Inversion of bit 1 at address when
one or two bytes are accessed
0: As-is
1: Inversion
C[i]CRDO0: Inversion of bit 0 at address when
one byte is accessed
0: As-is
1: Inversion
C[i]CRDO1 and C[i]CRDO0 function for endian
adjustment. Note that if an endian different from
the endian of this LSI is used, up to three
different addresses are accessed from the
address where the start and end addresses are
specified when an area is allocated.
• When the destination is the STIF (C[i]DA bit = 1)
C[i]CRDO3: Data swap in two-byte units
(longword swap in word units)
0: As-is
1: Swap
C[i]CRDO2: Data swap in one-byte units (word
swap in byte units)
0: As-is
1: Swap
C[i]CRDO1: Data swap in one-bit units (byte
swap in one-bit units)
0: As-is
1: Swap
C[i]CRDO0: Set this bit to 0 as reserved.
Rev. 1.00 Nov. 14, 2007 Page 508 of 1262
REJ09B0437-0100