SH7670 Datasheet, PDF (1114/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 26 High-Performance User Debugging Interface (H-UDI)
26.4.2 Reset Configuration
Table 26.4 Reset Configuration
ASEMD*¹
RES
TRST
Chip State
H
L
L
Power-on reset and H-UDI reset
H
Power-on reset
H
L
H-UDI reset only
H
Normal operation
L
L
L
Reset hold*²
H
Power-on reset
H
L
H-UDI reset only
H
Normal operation
Notes: 1. Performs normal mode and ASE mode settings
ASEMD = H, normal mode
ASEMD = L, ASE mode
2. In ASE mode, reset hold is entered if the TRST pin is driven low while the RES pin is
negated. In this state, the CPU does not start up. When TRST is driven high, H-UDI
operation is enabled, but the CPU does not start up. The reset hold state is cancelled
by a power-on reset.
Rev. 1.00 Nov. 14, 2007 Page 1088 of 1262
REJ09B0437-0100