SH7670 Datasheet, PDF (527/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Bit
Bit Name
0
C[i]C_E
Initial
Value R/W
0
R/W
Description
Execution Request
Setting this bit to 1 causes channel [i] processing to
be started. Setting this bit to 0 causes channel [i]
processing to be suspended. When 0 is written to
this bit, 0 is read immediately but the channel [i]
processor does not stop immediately. That is, the
processor stops after it writes back to the descriptor
being processed. To understand the channel
operating state, set the C[i]C_EIE bit to 1 to accept
the "operation end" interrupt request or poll the
"operation end" interrupt request flag. To start new
processing, the channel [i] of the STIF must be
initialized.
0: Channel [i] processing is halted.
1: Channel [i] processing is in progress.
Determine if channel [i] processing is suspended
when the processor writes back to the descriptor.
Rev. 1.00 Nov. 14, 2007 Page 501 of 1262
REJ09B0437-0100