SH7670 Datasheet, PDF (429/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 12 Ethernet Controller (EtherC)
Initial
Bit
Bit Name Value R/W
Description
0
PRM
0
R/W
Promiscuous Mode
Setting this bit enables all Ethernet frames to be
received. All Ethernet frames means all receivable
frames, irrespective of differences or enabled/disabled
status (destination address, broadcast address,
multicast bit, etc.).
0: EtherC performs normal operation
1: EtherC performs promiscuous mode operation
12.3.2 EtherC Status Register (ECSR)
ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can
be notified to the CPU by interrupts. When 1 is written to the PSRTO, LCHNG, MPD, and ICD,
the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that generate
interrupt, the interrupt can be enabled or disabled according to the corresponding bit in ECSIPR.
The interrupts generated due to this status register are indicated in the ECI bit in EESR.
Initial value: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
- PSRTO - LCHNG MPD ICD
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R/W
R
R/W R/W R/W
Rev. 1.00 Nov. 14, 2007 Page 403 of 1262
REJ09B0437-0100