SH7670 Datasheet, PDF (384/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 9 Clock Pulse Generator (CPG)
9.5.2 Changing the Division Ratio
Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is
not.
1. In the initial state, IFC = B'0 and PFC[2:0] = B'011.
2. Set the desired value in the IFC and PFC2 to IFC0 bits. The values that can be set are limited
by the clock operating mode and the multiplication rate of PLL circuit. Note that if the wrong
value is set, this LSI will malfunction.
3. After the register bits (IFC and PFC2 to PFC0) have been set, the clock is supplied of the new
division ratio.
Note: When executing the SLEEP instruction after the frequency has been changed, be sure to
read the frequency control register (FRQCR) three times before executing the SLEEP
instruction.
Rev. 1.00 Nov. 14, 2007 Page 358 of 1262
REJ09B0437-0100