SH7670 Datasheet, PDF (489/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit: _{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16}













RFF[2:0]
Initial Value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
R/W: _R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W
Bit: _{15 14 13 12 11 10}
9
8
7
6
5
4
3
2
1
0













RFD[2:0]
Initial Value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: _R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W
Bit
Bit Name
31 to 19 
Initial
value
All 0
18 to 16 RFF[2:0] 111
15 to 3 
All 0
2 to 0 RFD[2:0] 000
R/W
R
R/W

R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive Frame Number Flow Control Threshold
000: When one receive frame has been stored in the
receive FIFO
001: When two receive frames have been stored in the
receive FIFO
:
:
110: When seven receive frames have been stored in
the receive FIFO
111: When eight receive frames have been stored in
the receive FIFO
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive Byte Flow Control Threshold
000: When (256 − 64) bytes of data is stored in the
receive FIFO
001: When (512 − 64) bytes of data is stored in the
receive FIFO
Other than above: Setting prohibited
Rev. 1.00 Nov. 14, 2007 Page 463 of 1262
REJ09B0437-0100