SH7670 Datasheet, PDF (306/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
CKIO
A25 to A0
CExx
RD/WR
Read
Write
RD
D15 to D0
WE
D15 to D0
BS
WAIT
Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w
Figure 7.38 Wait Timing for PCMCIA Memory Card Interface
(TED[3:0] = B'0010, PCW[3:0] = B'0000, TEH[3:0] = B'0001, Hardware Wait = 1)
A port is used to generate the REG signal that switches between the common memory and
attribute memory. As shown in the example in figure 7.39, when the total memory space necessary
for the common memory and attribute memory is 32 Mbytes or less, pin A24 can be used as the
REG signal to allocate a 16-Mbyte common memory space and a 16-Mbyte attribute memory
space.
Rev. 1.00 Nov. 14, 2007 Page 280 of 1262
REJ09B0437-0100