SH7670 Datasheet, PDF (540/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
14.2.8 Channel [i] Processing Descriptor 2 Register (C[i]D2)
[Destination Address] (i = 0, 1)
Do not write any value to this register when C[i]C_E is set to 1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C[i]D2[31:16]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
Initial Value: ⁰
R/W: R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
7
C[i]D2[15:0]
0
0
R/W R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Bit Name
31 to 0 C[i]D2[31:0]
Initial
Value R/W
All 0 R/W
Description
Transfer Data Destination Address
Specify a destination address to which to write back
the transfer data.
When splitting continuous data into several
descriptors for execution, specify the same source
address in all the descriptors.
14.2.9 Channel [i] Processing Descriptor 3 Register (C[i]D3) [Data Length] (i = 0, 1)
Do not write any value to this register when C[i]C_E is set to 1.
Bit: 31

Initial Value: 0
R/W: R/W
30 29 28 27
 C[i]DWE C[i]DIE 
0
0
0
0
R/W R/W R/W R/W
26

0
R/W
25

0
R/W
24

0
R/W
23

0
R/W
22

0
R/W
21

0
R/W
20

0
R/W
19

0
R/W
18

0
R/W
17

0
R/W
16

0
R/W
Bit: 15
Initial Value: ⁰
R/W: R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
7
C[i]D3[15:0]
0
0
R/W R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Rev. 1.00 Nov. 14, 2007 Page 514 of 1262
REJ09B0437-0100