SH7670 Datasheet, PDF (380/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 9 Clock Pulse Generator (CPG)
9.4 Register Descriptions
The clock pulse generator has the following registers.
Table 9.4 Register Configuration
Register Name
Frequency control register
Abbreviation R/W
FRQCR
R/W
Initial Value Address Access Size
H'0003
H'FFFE0010 16
9.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the
CKIO pin during normal operation mode, software standby mode and standby mode cancellation.
The register also specifies the frequency-multiplier of the PLL circuit and the frequency division
ratio for the internal clock and peripheral clock (Pφ). FRQCR is accessed by word.
FRQCR is initialized to H'0003 only by a power-on reset or in deep standby. FRQCR retains its
previous value in manual reset or software standby mode. The previous value is also retained
when an internal reset is triggered by an overflow of the WDT.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
CKOEN[1:0]
-
-
STC[1:0]
-
-
-
IFC
-
PFC[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
R/W: R
R R/W R/W R
R R/W R/W R
R
R R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15, 14 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 14, 2007 Page 354 of 1262
REJ09B0437-0100