SH7670 Datasheet, PDF (523/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
14.1.3 Restrictions on the A-DMAC
The following restrictions apply to the A-DMAC:
• The A-DMAC supports only register access in 32-bit units.
• If the channel processor, or FEC processor is running, write to registers related to the
appropriate processor is inhibited. However, you can write data to the following two registers
by verifying them after the write even if the appropriate processor is running. Write data
repeatedly till verify succeeds.
 Channel [i] processing control register (C[i]C) (However, do not rewrite the C[i]C_R bit of
the running channel processor.)
 Channel [i] processing interrupt request register (C[i]I)
• Descriptors of data size 0 are inhibited.
Rev. 1.00 Nov. 14, 2007 Page 497 of 1262
REJ09B0437-0100