SH7670 Datasheet, PDF (713/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
3 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Notes: 1. To clear the status indicated by the bits in this register, write 0 only to the bits to be
cleared; write 1 to the other bits.
2. A change in the status indicated by the BCHG bit can be detected even while the clock
supply is stopped (while SCKE is 0), and the interrupt is output when the corresponding
interrupt enable bit is enabled. Clearing the status through software should be done
after enabling the clock supply.
No interrupts other than BCHG can be detected while the clock supply is stopped (while
SCKE is 0).
Rev. 1.00 Nov. 14, 2007 Page 687 of 1262
REJ09B0437-0100