SH7670 Datasheet, PDF (378/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 9 Clock Pulse Generator (CPG)
PLL
Frequency
Clock
Multiplier
Operating FRQCR
PLL
Mode
Setting*¹ Divider 1 Circuit
Ratio of
Internal
Clock
Frequencies
(I:B:P)*²
Input Clock*³
Selectable Frequency Range (MHz)
Output Clock Internal Clock Bus Clock
(CKIO Pin)
(Iφ)
(Bφ)
Peripheral
Clock (Pφ)
2
H'x003 1/4
ON (× 8) 2:1:1/2
60.00 to 100.00 
H'x004 1/4
ON (× 8)
2:1:1/3
60.00 to 100.00 
H'x005 1/4
ON (× 8)
2:1:1/4
60.00 to 100.00 
H'x006 _1/4
ON (× 8) 2:1:1/6
60.00 to 100.00 
120.00 to 200.00 60.00 to 100.00 30.00 to 50.00
120.00 to 200.00 60.00 to 100.00 20.00 to 33.33
120.00 to 200.00 60.00 to 100.00 15.00 to 25.00
120.00 to 200.00 60.00 to 100.00 10.00 to 16.67
H'x013 1/4
ON (× 8) 1:1:1/2
60.00 to 100.00 
60.00 to 100.00 60.00 to 100.00 30.00 to 50.00
H'x014 1/4
ON (× 8) 1:1:1/3
60.00 to 100.00 
60.00 to 100.00 60.00 to 100.00 20.00 to 33.33
H'x015 1/4
ON (× 8) 1:1:1/4
60.00 to 100.00 
60.00 to 100.00 60.00 to 100.00 15.00 to 25.00
H'x016 1/4
ON (× 8) 1:1:1/6
60.00 to 100.00 
60.00 to 100.00 60.00 to 100.00 10.00 to 16.67
H'x104 1/4
H'x106 1/4
ON (× 12)
ON (× 12)
3:1:1/2
3:1:1/4
60.00 to 66.67 
60.00 to 66.67 
180.00 to 200.00 60.00 to 66.67 30.00 to 33.33
180.00 to 200.00 60.00 to 66.67 15.00 to 16.67
3
H'x003 1/2
ON (× 8) 4:2:1
48.00 to 48.00 96.00 to 96.00 192.00 to 192.00 96.00 to 96.00 48.00 to 48.00
H'x004 1/2
ON (× 8)
4:2:2/3
48.00 to 48.00 96.00 to 96.00 192.00 to 192.00 96.00 to 96.00 32.00 to 32.00
H'x005 1/2
ON (× 8)
4:2:1/2
48.00 to 48.00 96.00 to 96.00 192.00 to 192.00 96.00 to 96.00 24.00 to 24.00
H'x006 1/2
ON (× 8) 4:2:1/3
48.00 to 48.00 96.00 to 96.00 192.00 to 192.00 96.00 to 96.00 16.00 to 16.00
H'x013 1/2
ON (× 8) 2:2:1
48.00 to 48.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 48.00 to 48.00
H'x014 1/2
ON (× 8) 2:2:2/3
48.00 to 48.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 32.00 to 32.00
H'x015 1/2
ON (× 8) 2:2:1/2
48.00 to 48.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 24.00 to 24.00
H'x016 1/2
ON (× 8) 2:2:1/3
48.00 to 48.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 16.00 to 16.00
Notes:
1. x in the FRQCR register setting depends on the set value in bits 12 and 13.
2. The ratio of clock frequencies, where the input clock frequency is assumed to be 1.
3. In mode 0, the frequency of the EXTAL pin input clock or the crystal resonator
In mode 1, the frequency of the EXTAL pin input clock
In mode 2, the frequency of the CKIO pin input clock.
In mode 3, the frequency of the USB_X1 pin input clock or the crystal resonator
Cautions: 1. The frequency of the internal clock is as follows:
In mode 0 the frequency on the EXTAL pin × the frequency-multiplier of the PLL
circuit × the divisor of the divider 1
In mode 1 (the frequency on the EXTAL pin × 1/2) × the frequency-multiplier of
the PLL circuit × the divisor of the divider 1
Rev. 1.00 Nov. 14, 2007 Page 352 of 1262
REJ09B0437-0100