SH7670 Datasheet, PDF (588/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
15.3.9 STIFPWM Control Register (STPWMCR)
STPWMCR is a 32-bit register that specifies the generation of write pulses of the internal PCR
and STC registers. STPWMCR is initialized to H'00000000 by a power-on reset.
Bit Bit Name
31 to 9 
Initial
Value R/W
All 0 R
8
STCXP
0
R/W
7
PWMBRS 0
R/W
6
PWMBWP 0
R/W
5
PWMRS 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Setting this bit to 1 causes the STC value to be
transferred to STSTC0R and STSTC1R.
This bit is automatically cleared to 0.
Setting this bit to 1 causes the internal PWM register
value to be transferred to STPWM (PWMB).
This bit is automatically cleared to 0.
Setting this bit to 1 causes the STPWM (PWMB) value to
be reflected in PWM.
PWM control is immediately performed with the value that
is set in PWM. Loading with this bit can preferentially be
performed independently of the PWMSEL and PWMUEN
settings, except when the PWM control variable is an
invalid value as described in the UNZF bit field of STSTR.
If this bit is set to 1 together with the PWMWP bit,
PWMBWP takes precedence.
This bit is automatically cleared to 0.
Setting this bit to 1 causes the difference (internal STC -
internal PCR) result to be transferred to STPWM (PWM).
The difference result is masked by the PWMCYC bits
(validity comparison bits) of STPWMMR as shown in
figure 15.9.
This bit is automatically cleared to 0.
Rev. 1.00 Nov. 14, 2007 Page 562 of 1262
REJ09B0437-0100