SH7670 Datasheet, PDF (460/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 12 Ethernet Controller (EtherC)
12.4.6 Operation by IPG Setting
The EtherC has a function to change the non-transmission period IPG (Inter Packet Gap) between
transmit frames. By changing the set values of the IPG setting register (IPGR), the transmission
efficiency can be raised and lowered from the standard value. IPG settings are prescribed in
IEEE802.3 standards. When changing settings, adequately check that the respective devices can
operate smoothly on the same network.
Case A
(short IPG)
[1]
[2]
[3]
[4]
[5]
......
Packet IPG*
Case B
(long IPG)
[1]
[2]
[3]
[4]
......
Note: * IPG may be longer than the set value, depending on the state of the circuit and the system bus.
Figure 12.7 Changing IPG and Transmission Efficiency
12.4.7 Flow Control
The EtherC supports flow control functions conforming to IEEE802.3x in full-duplex operations.
Flow control can be applied to both receive and transmit operations. The methods for transmitting
PAUSE frames when controlling flow are as follows:
Automatic PAUSE Frame Transmission: For receive frames, PAUSE frames are automatically
transmitted when the number of data in the receive FIFO (included in E-DMAC) reaches the value
set in the flow control FIFO threshold register (FCFTR) of the E-DMAC. The TIME parameter
included in the PAUSE frame at this time is set by the automatic PAUSE frame setting register
(APR). The automatic PAUSE frame transmission is repeated until the number of data in the
receive FIFO becomes less than the FCFTR setting as the receive data is read from the FIFO.
The upper limit of the number of retransfers of the PAUSE frame can also be set by the automatic
PAUSE frame retransfer count set register (TPAUSER). In this case, PAUSE frame transmission
is repeated until the number of data becomes FCFTR value set or below, or the number of
transmits reaches the value set by TPAUSER. The automatic PAUSE frame transmission is
enabled when the TXF bit in the EtherC mode register (ECMR) is 1.
Rev. 1.00 Nov. 14, 2007 Page 434 of 1262
REJ09B0437-0100