SH7670 Datasheet, PDF (476/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)
EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual
bits in the EtherC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the
corresponding bit. In the initial state, interrupts are not enabled.
Bit: 31 30 29
 TWBIP 
Initial Value: 0
0
0
R/W: R R/W R
Bit: 15 14 13



Initial Value: 0
0
0
R/W: R
R
R
28 27 26 25 24 23 22 21 20 19 18 17 16


TABTIP
RABTIP
RFCOF
IP
ADEIP
ECIIP
TCIP
TDEIP TFUFIP FRIP RDEIP RFOFIP
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W
12 11 10 9
8
7
6
 CNDIP DLCIP CDIP TROIP RMAFIP 
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R
5
4
3
2
1
0
 RRFIP RTLFIP RTSFIP PREIP CERFIP
0
0
0
0
0
0
R R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value
31

0
30
TWBIP
0
29 to 27 
All 0
26
TABTIP 0
25
RABTIP 0
24
RFCOFIP 0
R/W Description
R Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Write-Back Complete Interrupt Permission
0: Write-back complete interrupt is disabled
1: Write-back complete interrupt is enabled
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit Abort Detection Interrupt Permission
0: Transmit abort detection interrupt is disabled
1: Transmit abort detection interrupt is enabled
R/W Receive Abort Detection Interrupt Permission
0: Receive abort detection interrupt is disabled
1: Receive abort detection interrupt is enabled
R/W Receive Frame Counter Overflow Interrupt Permission
0: Receive frame counter overflow interrupt is disabled
1: Receive frame counter overflow interrupt is enabled
Rev. 1.00 Nov. 14, 2007 Page 450 of 1262
REJ09B0437-0100