SH7670 Datasheet, PDF (379/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 9 Clock Pulse Generator (CPG)
In mode 2 (the frequency on the CKIO pin × 1/4) × the frequency-multiplier of
the PLL circuit × the divisor of the divider 1
In mode 3 (the frequency on the USB_X1pin × 1/2) × the frequency-multiplier of
the PLL circuit × the divisor of the divider 1
The frequency of the internal clock should not be set lower than the frequency on the
CKIO pin.
2. The frequency of the peripheral clock is as follows:
In mode 0
In mode 1
the frequency on the EXTAL pin × the frequency-multiplier of the PLL
circuit × the divisor of the divider 1
(the frequency on the EXTAL pin × 1/2) × the frequency-multiplier of
the PLL circuit × the divisor of the divider 1
In mode 2 (the frequency on the CKIO pin × 1/4) × the frequency-multiplier of
the PLL circuit × the divisor of the divider 1
In mode 3 (the frequency on the USB_X1 pin × 1/2) × the frequency-multiplier of
the PLL circuit × the divisor of the divider 1
The frequency of the peripheral clock should be set to 50 MHz or less, and should
not be set higher than one half of the frequency on the CKIO pin.
3. The frequency multiplier of PLL circuit can be selected as ×8 or × 12. The divisor of
the divider can be selected as × 1, × 1/2, × 1/3, × 1/4, × 1/6, × 1/8, or × 1/12. The
settings are made in the frequency-control register (FRQCR).
4. The output frequency of the PLL circuit is as follows:
In mode 0 the frequency on the EXTAL pin × the frequency-multiplier of the PLL
circuit
In mode 1 (the frequency on the EXTAL pin × 1/2) × the frequency-multiplier of
the PLL circuit
In mode 2 (the frequency on the CKIO pin × 1/4) × the frequency-multiplier of
the PLL circuit
In mode 3 (the frequency on the USB_X1 pin × 1/2) × the frequency-multiplier of
the PLL circuit
Ensure that the output frequency of the PLL circuit should be 200 MHz or less.
Rev. 1.00 Nov. 14, 2007 Page 353 of 1262
REJ09B0437-0100