SH7670 Datasheet, PDF (1267/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 29 Electrical Characteristics
29.4.18 STIF Module Signal Timing (4)
(With Stream Input/Output Set Synchronized with STn_CLKIN Fall Time)
Table 29.24 STIF Module Signal Timing (4)
Conditions:
V_CC = V_CC (PLL) = DV12 = UV12 = 1.1 to 1.3 V, V_CCQ = DV33 = 3.1 to 3.5 V,
AV12 = 1.1 to 1.3 V, AV33 = 3.1 to 3.5 V,
V_SS = V_SS (PLL) = DG12 = UG12 = V_SSQ = DG33 = AG12 = AG33 = 0 V,
Ta = –20 to 70°C (regular specifications),
–40 to 85°C (wide temperature specifications)
Item
STn_SYC output delay time 2
STn_VLD output delay time 2
STn_REQ output delay time 2
STn_Dm output delay time 2
STn_SYC input setup time 2
STn_SYC input hold time 2
STn_VLD input setup time 2
STn_VLD input hold time 2
STn_REQ input setup time 2
STn_REQ input hold time 2
STn_Dm input setup time 2
STn_Dm input hold time 2
Symbol
t
STSD2
t_STVD2
t_STRD2
t
STDD2
t
STSS2
t
STSH2
t
STVS2
t_STVH2
t
STRS2
t_STRH2
t_STDS2
t_STDH2
Min.




4
6
4
6
4
6
4
6
Max.
Unit
11
ns
11
ns
11
ns
11
ns

ns

ns

ns

ns

ns

ns

ns

ns
Figure
29.71
Rev. 1.00 Nov. 14, 2007 Page 1241 of 1262
REJ09B0437-0100