SH7670 Datasheet, PDF (154/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 5 Exception Handling
5.8 Stack Status after Exception Handling Ends
The status of the stack after exception handling ends is as shown in table 5.12.
Table 5.12 Stack Status After Exception Handling Ends
Exception Type
Address error
Stack Status
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Interrupt
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Register bank error (overflow)
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Register bank error (underflow)
SP
Start address of relevant
RESBANK instruction
SR
32 bits
32 bits
Trap instruction
SP
Address of instruction
after TRAPA instruction
SR
32 bits
32 bits
Slot illegal instruction
SP
Jump destination address
of delayed branch instruction
32 bits
SR
32 bits
Rev. 1.00 Nov. 14, 2007 Page 128 of 1262
REJ09B0437-0100