SH7670 Datasheet, PDF (923/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.6 Interface
20.6.1 Basic Sequence
Figure 20.3 shows the basic read/write sequence. HIF read is defined by the overlap period of the
HIFRD low-level period and HIFCS low-level period, and HIF write is defined by the overlap
period of the HIFWR low-level period and HIFCS low-level period. The HIFRS signal indicates
whether this is normal access or index register access; low level indicates normal access and high
level indicates index register access.
HIFCS
HIFRS
HIFRD
HIFWR
HIFD15 to HIFD00
Write cycle
Read cycle
WT_D
RD_D
Figure 20.3 Basic Timing for HIF Interface
Rev. 1.00 Nov. 14, 2007 Page 897 of 1262
REJ09B0437-0100