SH7670 Datasheet, PDF (350/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 8 Direct Memory Access Controller (DMAC)
Choose to detect DREQ by either the edge or level of the signal input with the DL and DS bits in
CHCR_0 and CHCR_1 as shown in table 8.6. The source of the transfer request does not have to
be the data transfer source or destination. Upon detection of a rising or falling edge, one transfer
request in burst mode causes the transfer to continue until DMATCR = 0 is reached. In cycle steal
mode, one transfer request results in a single transfer.
Table 8.6 Selecting External Request Detection with DL and DS Bits
DL bit
0
1
CHCR
DS bit
0
1
0
1
Detection of External Request
Low level detection
Falling edge detection
High level detection
Rising edge detection
When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive
period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again
enters the request accept enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
Overrun 0: Transfer is terminated after the same number of transfer has been performed as
requests.
Overrun 1: Transfer is terminated after transfers have been performed for (the number of requests
plus 1) times.
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 8.7 Selecting External Request Detection with DO Bit
CHCR
DO bit
0
1
External Request
Overrun 0
Overrun 1
Rev. 1.00 Nov. 14, 2007 Page 324 of 1262
REJ09B0437-0100